Strained Si1-xGex with a mid-level Ge content of approximately 0.5 is a viable candidate for small geometry devices (e.g., 7 nm) and beyond. The Ge level is sufficient, as far as leakage considerations are concerned, for fabricating high-performance devices. In addition, the charge carrier mobility is theoretically adequate with a reasonable strain, which can be achieved by growing the Si1-xGex material on a strain relaxed buffer (SRB) or on strained Si direct on insulator (SSDOI).
In this environment the equivalent inversion capacitance oxide thickness (CETinv or Tinv) becomes an important consideration for achieving an aggressive gate length that is needed with tightly contacted gate pitches.